Please refer to FIG. 1, which is a schematic diagram showing a conventional double data rate synchronous dynamic random access memory (DDR SDRAM) device 10 having latency control for a column-command address thereof. As shown, the DDR SDRAM device includes a read-command decoder 121, an address input buffer 122, a write-command decoder 123, a mode register 124, a processing device 13, a column address decoder 14 and a memory array 15. The memory array 15 is a DDR SDRAM array including plural memory cells (not shown) disposed into rows and columns. The column address decoder 14 receives an address signal LDS1 output from the processing device 13, and produces a driving signal CSL1 used for controlling the memory array 15, wherein the address signal LDS1 includes a column-command address AS1 used for pointing at a specific memory cell of the plural memory cells.
The processing device 13 includes a read-address latch device 131, a write-address register 132 and a latch unit 133. The input terminal 133A of the latch unit 133 is electrically connected to the output terminal 131B of the read-address latch device 131 and the output terminal 132B of the write-address register 132, and the input terminal 133A of the latch unit 133 has an address signal KDS1.
The mode register 124 receives a mode register set command MRS1 to produces a write latency WL1 being a value. The address input buffer 122 receives an input address signal CDS1 and produces an internal address signal IDS1, wherein the internal address signal IDS1 is lagged behind the input address signal CDS1 by a buffer delay time.
A read operation of the DDR SDRAM device 10 is taken as an example. In a first clock period, the read-command decoder 121 receives a read command RCM1 and the address input buffer 122 receives the column-command address AS1, which corresponds to the read command RCM1, of the input address signal CDS1. The read-command decoder 121 produces a read timing signal CKR1 in response to the read command RCM1. The read-address latch device 131 contributes to the address signal KDS1 in response to the read timing signal CKR1 and the internal address signal IDS1. The latch unit 133 receives the address signal KDS1 and produces the address signal LDS1. Each of the input address signal CDS1, the internal address signal IDS1, the address signal KDS1 and the address signal LDS1 includes the column-command address AS1, but the time points that the column-command address AS1 is loaded into those signals are different.
A write operation of the DDR SDRAM device 10 is taken as an example. In a second clock period, the write-command decoder 123 receives a write command WCM1 and the address input buffer 122 receives a column-command address AS2, corresponding to the write command WCM1, of the input address signal CDS1. The write-command decoder 123 produces a write timing signal CKW1 in response to the write command WCM1. The write-address register 132 contributes to the address signal KDS1 in response to the write timing signal CKW1 and the internal address signal IDS1 and the write latency WL1. The latch unit 133 receives the address signal KDS1 and produces the address signal LDS1.
Please refer to FIG. 2, which is a schematic diagram showing a circuit of the processing device 13 in FIG. 1. As shown, the processing device 13 includes the read-address latch device 131, the write-address register 132 and the latch unit 133. The read-address latch device 131 includes two switches 21 and 22, a NOT gate 1311 and a latch unit 31. The NOT gate 1311 receives the read timing signal CKR1 and produces a signal BCLKR1. The input terminal 21A of the switch 21 receives the internal address signal IDS1; the control terminal 21C of the switch 21 receives the read timing signal CKR1; the input terminal 31A of the latch unit 31 is electrically connected to the output terminal 21B of the switch 21. The input terminal 22A of the switch 22 is electrically connected to the output terminal 31B of the latch unit 31; the control terminal 22C of the switch 22 receives the signal BCKR1; the output terminal 22B of the switch 22 contributes to the address signal KDS1. The switch 21 includes a transmission gate 211 and a NOT gate. The latch unit 31 includes a NOT gate 311 and a NOT gate 312 connected in parallel with the NOT gate 311 in the state of the opposite direction thereof. The switches 21 and 22 have the same structure.
The read timing signal CKR1 has a low logical level in a first time interval, e.g. the first time interval is in the first clock period. In the first time interval, the column-command address AS1 of the internal address signal IDS1 is written into the latch unit 31 through the transmission gate 211. The read timing signal CKR1 has a high logical level in a second time interval following the first time interval. In the second time interval, the column-command address AS1 at the output terminal 31B of the latch unit 31 is written into the latch unit 133 through the transmission gate 221, which causes the address signal LDS1 to carry the column-command address AS1.
The write-address register 132 includes a NOT gate 1321, six switches 23, 24, 25, 26, 27 and 28, five latch units 32, 33, 34, 35 and 36, and a multiplexing device 39. The five latch units 32, 33, 34, 35 and 36 and the six switches 23, 24, 25, 26, 27 and 28 are connected in series in the sequence of the component references 23, 32, 24, 33, 25, 34, 26, 35, 27, 36 and 28. The NOT gate 1321 receives the write timing signal CKW1 and produces a signal BCKW1. The input terminal 23A of the switch 23 receives the internal address signal IDS1; each of the control terminal 23C of the switch 23, the control terminal 25C of the switch 25 and the control terminal 27C of the switch 27 receives the signal BCKW1; the output terminal 24B of the switch 24, the output terminal 26B of the switch 26 and the output terminal 28B of the switch 28 produce plural signals JS11, JS12 and JS13 respectively, wherein the signal JS12 is lagged behind the signal JS11 by a clock period, and the signal JS13 is lagged behind the signal JS12 by a clock period.
The write timing signal CKW1 has three sequential low logical levels in a third, a fourth and a fifth time intervals. In the third, the fourth and the fifth time intervals, the internal address signal IDS1, the latch unit 33 and the latch unit 35 have the column-command address AS2 respectively. In the third, the fourth and the fifth time intervals, the column-command address AS2 is sequentially written into the latch units 32, 34 and 36 through the switches 23, 25 and 27. The write timing signal CKW1 has three sequential high logical levels in a sixth, a seventh and an eighth time intervals. In the sixth, the seventh and the eighth time intervals, the latch units 32, 34 and 36 have the column-command address AS2 respectively. In the sixth, the seventh and the eighth time intervals, the column-command address AS2 is sequentially written into the latch unit 33, the latch unit 35 and the output terminal 28B of the switch 28 through the switches 24, 26 and 28, wherein the third, the six, the fourth, the seventh, the fifth and the eighth time intervals are six sequential time intervals.
The multiplexing device 39 receives the write latency WL1 and the signals JS1, JS12 and JS13, and selects one of the signals JS1, JS12 and JS13 to contribute to the address signal KDS1 according to the write latency WL1. The latch unit 133 receives the address signal KDS1 and produces the address signal LDS1. When the value of the write latency WL1 is changed, the time point to load the column-command address AS2 into the address signal LDS1 can also be changed.
In FIG. 1 and FIG. 2, the DDR SDRAM device 10 uses shift registers to control the column-command address AS1 and the column-command address AS2, which corresponds to the read command RCM1 and the write command WCM1 respectively. Because the latency of the read operation is different from that of the write operation, two different register paths are necessary for the read operation and the write operation. Therefore, how to further integrate the two different register paths for simplifying the column-command address control becomes the requirement on the development.